// ****************************************************************************** 
// Copyright     :  Copyright (C) 2018, Hisilicon Technologies Co. Ltd.
// File name     :  glb_cfg_axi_reg_offset_field.h
// Project line  :  K3
// Department    :  K3
// Author        :  Huawei
// Version       :  V100
// Date          :  2015/4/10
// Description   :  HiVcodecV100 VDEC
// Others        :  Generated automatically by nManager V4.2 
// History       :  Huawei 2018/04/10 10:02:42 Create file
// ******************************************************************************

#ifndef __GLB_CFG_AXI_REG_OFFSET_FIELD_H__
#define __GLB_CFG_AXI_REG_OFFSET_FIELD_H__

#define GLB_CFG_AXI_ACFG2ARB_MID_EN_LEN    1
#define GLB_CFG_AXI_ACFG2ARB_MID_EN_OFFSET 12
#define GLB_CFG_AXI_ACFG2ARB_ROSD_LEN      8
#define GLB_CFG_AXI_ACFG2ARB_ROSD_OFFSET   4
#define GLB_CFG_AXI_ACFG2ARB_WOSD_LEN      4
#define GLB_CFG_AXI_ACFG2ARB_WOSD_OFFSET   0

#define GLB_CFG_AXI_ALL_R_ARBIT_MID_RRMAX4_LEN    5
#define GLB_CFG_AXI_ALL_R_ARBIT_MID_RRMAX4_OFFSET 20
#define GLB_CFG_AXI_ALL_R_ARBIT_MID_RRMAX3_LEN    5
#define GLB_CFG_AXI_ALL_R_ARBIT_MID_RRMAX3_OFFSET 15
#define GLB_CFG_AXI_ALL_R_ARBIT_MID_RRMAX2_LEN    5
#define GLB_CFG_AXI_ALL_R_ARBIT_MID_RRMAX2_OFFSET 10
#define GLB_CFG_AXI_ALL_R_ARBIT_MID_RRMAX1_LEN    5
#define GLB_CFG_AXI_ALL_R_ARBIT_MID_RRMAX1_OFFSET 5
#define GLB_CFG_AXI_ALL_R_ARBIT_MID_RRMAX0_LEN    5
#define GLB_CFG_AXI_ALL_R_ARBIT_MID_RRMAX0_OFFSET 0

#define GLB_CFG_AXI_CFG_BG_KIND_LEN    2
#define GLB_CFG_AXI_CFG_BG_KIND_OFFSET 0

#define GLB_CFG_AXI_VDH_FORCE_REQ_ACK_LEN    1
#define GLB_CFG_AXI_VDH_FORCE_REQ_ACK_OFFSET 1
#define GLB_CFG_AXI_BPD_FORCE_REQ_ACK_LEN    1
#define GLB_CFG_AXI_BPD_FORCE_REQ_ACK_OFFSET 0

#define GLB_CFG_AXI_SEL_SIGNAL_LEN      4
#define GLB_CFG_AXI_SEL_SIGNAL_OFFSET   28
#define GLB_CFG_AXI_CH0_SIGNAL_LEN      4
#define GLB_CFG_AXI_CH0_SIGNAL_OFFSET   24
#define GLB_CFG_AXI_CH1_SIGNAL_LEN      4
#define GLB_CFG_AXI_CH1_SIGNAL_OFFSET   20
#define GLB_CFG_AXI_CH2_SIGNAL_LEN      4
#define GLB_CFG_AXI_CH2_SIGNAL_OFFSET   16
#define GLB_CFG_AXI_CH3_SIGNAL_LEN      4
#define GLB_CFG_AXI_CH3_SIGNAL_OFFSET   12
#define GLB_CFG_AXI_CUR_RCMD_ST_LEN     4
#define GLB_CFG_AXI_CUR_RCMD_ST_OFFSET  8
#define GLB_CFG_AXI_RCMD_CHN_CNT_LEN    7
#define GLB_CFG_AXI_RCMD_CHN_CNT_OFFSET 0

#define GLB_CFG_AXI_SEL_SIGNAL_LEN        6
#define GLB_CFG_AXI_SEL_SIGNAL_OFFSET     26
#define GLB_CFG_AXI_CH0_SIGNAL_LEN        6
#define GLB_CFG_AXI_CH0_SIGNAL_OFFSET     20
#define GLB_CFG_AXI_CH1_SIGNAL_LEN        6
#define GLB_CFG_AXI_CH1_SIGNAL_OFFSET     14
#define GLB_CFG_AXI_WCMD_B_CHN_CNT_LEN    6
#define GLB_CFG_AXI_WCMD_B_CHN_CNT_OFFSET 6
#define GLB_CFG_AXI_WCMD_CHN_CNT_LEN      2
#define GLB_CFG_AXI_WCMD_CHN_CNT_OFFSET   4
#define GLB_CFG_AXI_CUR_WCMD_ST_LEN       3
#define GLB_CFG_AXI_CUR_WCMD_ST_OFFSET    0

#define GLB_CFG_AXI_BUS_VALID_SIG_LEN    8
#define GLB_CFG_AXI_BUS_VALID_SIG_OFFSET 24
#define GLB_CFG_AXI_CBB_VALID_SIG_LEN    8
#define GLB_CFG_AXI_CBB_VALID_SIG_OFFSET 16
#define GLB_CFG_AXI_CBB_READY_SIG_LEN    8
#define GLB_CFG_AXI_CBB_READY_SIG_OFFSET 8
#define GLB_CFG_AXI_BUS_READY_SIG_LEN    8
#define GLB_CFG_AXI_BUS_READY_SIG_OFFSET 0

#define GLB_CFG_AXI_BUS_AXI_RST_ACK_LEN    1
#define GLB_CFG_AXI_BUS_AXI_RST_ACK_OFFSET 29
#define GLB_CFG_AXI_BUS_AXI_RST_REQ_LEN    1
#define GLB_CFG_AXI_BUS_AXI_RST_REQ_OFFSET 28
#define GLB_CFG_AXI_SRCR_CUR_FSM_LEN       2
#define GLB_CFG_AXI_SRCR_CUR_FSM_OFFSET    26
#define GLB_CFG_AXI_SRCW_CUR_FSM_LEN       2
#define GLB_CFG_AXI_SRCW_CUR_FSM_OFFSET    24
#define GLB_CFG_AXI_WR_AW_WLAST_CNT_LEN    6
#define GLB_CFG_AXI_WR_AW_WLAST_CNT_OFFSET 16
#define GLB_CFG_AXI_WR_CNT_LEN             6
#define GLB_CFG_AXI_WR_CNT_OFFSET          8
#define GLB_CFG_AXI_RD_CNT_LEN             7
#define GLB_CFG_AXI_RD_CNT_OFFSET          0

#endif // __GLB_CFG_AXI_REG_OFFSET_FIELD_H__
